Seminar Formal Verification

Semester: 
Modul: 
CS3702,
CS5840,
CS5480,
CS5015,
CS5191

In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics. [Wikipedia]

We particularily consider the verification of software systems including their modelling on different levels of abstraction and the specification of properties that are to be verified. Typical approaches are, for example theorem proving, testing, model checking, runtime verification, static analysis and type checking. They rely on formal concepts such as (temporal) logic, automata- and game theory or process algebras. The major goal is an automatic comparisson of the (possibly abstract) modell and a property specification.

WS 2014/2015
Preliminary meeting (Vorbesprechung)
Friday 13:00-13:40 1.108 (Besprechungsraum ISP), Building 64 (not every week)

Abstract and outline
Wednesday 23:59-23:59 submission deadline (not every week)

Report final version
Monday 23:59-23:59 submission deadline (not every week)

Presentation material (slides) final version
Monday 23:59-23:59 submission deadline (not every week)

Preliminary meeting (Vorbesprechung)
Friday July 25, 2014 13:00-13:40 (1.108 (Besprechungsraum ISP), Building 64)

Abstract and outline
Wednesday October 8, 2014 23:59-23:59 (submission deadline)

Report final version
Monday December 1, 2014 23:59-23:59 (submission deadline)

Presentation material (slides) final version
Monday December 8, 2014 23:59-23:59 (submission deadline)

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